ASIC Digital Designer (EP-ESE-ME-2025-85-LD)

Company Description

At CERN, the European Organization for Nuclear Research, physicists and engineers are probing the fundamental structure of the universe. Using the world's largest and most complex scientific instruments, they study the basic constituents of matter - fundamental particles that are made to collide together at close to the speed of light. The process gives physicists clues about how particles interact, and provides insights into the fundamental laws of nature. Find out more on http://home.cern.

Job Description

Introduction

We are looking for a talented and experienced ASIC Digital Designer with expertise in digital-on-top (DoT) implementation and System-on-Chip (SoC) design techniques. The candidate will contribute to the development of ASICs for particle physics experiments, working with advanced planar CMOS technologies (e.g., 65nm, 28nm) in collaboration with system architects, analogue and mixed signal design teams and verification engineers.

You will join the Electronic Systems for Experiments Group (ESE) of the Experimental Physics Department (EP), which designs electronic systems, including ASICs, for the experiments at CERN and also supplies a series of electronics related services. The Microelectronics section (ME) develops analogue and digital application-specific integrated circuits for the readout and control of CERN's particle detector systems.

Functions

As an ASIC Digital Designer you will:

• Perform full-chip digital integration and verification:
  • incorporate custom logic, third party IP blocks and standard interfaces
  • manage clock/reset domains
  • apply low power design techniques
• Develop RTL code ensuring synthesizable and reusable designs.
• Develop high level architectures for ASIC designs, including SoC partitioning, data paths, control logic and interfaces.
• Write testbenches and run simulations to verify design functionality.

Qualifications

Master's degree or PhD or equivalent relevant experience in the field of Electronics Engineering or a related field.

Experience:

The experience required for this post is:

• Demonstrated experience in hierarchical Digital-On-Top ASIC integration and implementation (from RTL to GDS) including functional and physical verification.
• Proven experience with advanced EDA tools and deep submicron CMOS technologies, including Cadence tools and process nodes such as 65nm, 28nm, or smaller.
• Experience in RTL design (Verilog/SystemVerilog) and scripting languages (Python, TCL, and Shell) for workflow automation.
• Experience in performing, Logic Synthesis, Timing Closure, Static Timing Analysis, and Power Integrity Analysis.
• Experience in physical design floor planning, cell placement, routing and sign-off checks (DRC, LVS).
• Experience in developing test benches for conducting behavioural and functional simulations.
• Knowledge in integrating Analog and Digital IPs, managing interconnects, planning clock/reset domains and assigning timing constraints.
• Knowledge in integrating design-for-testability (DFT) structures (scan chains, BIST, JTAG) and employing design-for-manufacturing (DFM) methodologies.

Experience in the following fields will also be valued:

• Understanding of System-on-Chip (SoC) design techniques, including bus protocols (AXI, AHB, APB).
• Knowledge of RISC-V ISA and experience with RISC-V core integration.
• Experience with Microarchitecture design: fSMs, pipelining, ALUs, memory controllers.
• Experience with Debugging and linting tools (Verilator, etc.).
• Experience with FPGA prototyping for SoC validation.
• Experience in the use of design methodologies for the mitigation of radiation effects (SEE and TID) in digital CMOS circuits.

Technical competencies:

• Design and simulation of digital microelectronic circuits.
• Knowledge and application of high-level description languages and tools.
• Knowledge and application of signal integrity techniques.
• Testing and measurement of digital microelectronic circuits.

Behavioural competencies:

• Working in Teams: understanding when teamwork is required to achieve the best results; including others accordingly and sharing information.
• Achieving Results: having a structured and organised approach towards work; being able to set priorities and plan tasks with results in mind.
• Demonstrating Flexibility: adapting quickly and resourcefully to shifting priorities and requirements.
• Communicating Effectively: checking to ensure that the message has been well understood. Ensuring that information, procedures and decisions are appropriately documented.
• Learning and Sharing Knowledge: keeping up-to-date with developments in own field of expertise and readily absorbing new information; sharing knowledge and expertise freely and willingly with others; coaching others to ensure knowledge transfer.

Language skills:

Spoken and written English, with a commitment to learn French.

Additional Information

Eligibility and closing date:

Diversity has been an integral part of CERN's mission since its foundation and is an established value of the Organization. Employing a diverse workforce is central to our success. We welcome applications from all Member States and Associate Member States.

This vacancy will be filled as soon as possible, and applications should normally reach us no later than 25.05.02025 23:59 CEST.

Employment Conditions

Contract type: Limited duration contract (5 years). Subject to certain conditions, holders of limited-duration contracts may apply for an indefinite position.

Working Hours: 40 hours per week

This position involves:

• Work in Radiation Areas.
• Work during nights, Sundays and official holidays, when required by the needs of the Organization.

Job grade: 6-7

Job reference: EP-ESE-ME-2025-85-LD

Benchmark Job Title: Electronics Engineer

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